B. Tech in Semiconductor Engineering
Semiconductors are the invisible engines powering the modern world. From Artificial Intelligence, electric mobility, and smart manufacturing to defence systems, space technologies, and next-generation communication, semiconductors form the backbone of every advanced technological ecosystem.
Apply for admissions 2026.
Eligibility Criteria
Passed 10+2 examination with physics and mathematics and one of the subjects from the following Chemistry /Computer Science / Electronics /Information Technology /Biology/Informatics Practices / Biotechnology / Technical Vocational subject/Agriculture/Engineering Graphics/ Business Studies/ Entrepreneurship and obtained at least 50% marks (at least 45% marks, in case of candidates belonging to reserved category, EWS & PWD candidates belonging to Maharashtra state only) in the above subjects taken together.
OR
Should have passed a minimum of 3 years Diploma in Engineering and Technology and obtained at least 50% marks (at least 45% marks, in case of reserved categories, EWS & PWD Students belonging to Maharashtra state only)
(The Universities will offer suitable bridge courses such as Mathematics, Physics, Engineering drawing, etc., for the students coming from diverse backgrounds to prepare a Level playing field and desired learning outcomes of the programme). 2nd year, in case the vacancies at lateral entry are exhausted.
AND
Qualifying score in JEE OR MHT-CET OR any other State level Engineering Entrance Exam OR National-level Engineering Entrance Exam OR Common University Entrance Test (CUET) OR Symbiosis Engineering Entrance Test (SEET) conducted by SSPU OR Symbiosis International (Deemed) University’s SET Score and Candidate also need to appear for a counselling session.
Candidates will be selected based on their performance in the entrance test conducted by SSPU.
Passed 10+2 examination with Physics and Mathematics as compulsory subjects along with one of the Chemistry or Biotechnology or Biology or Technical Vocational subject or Computer Science or Information Technology or Informatics Practices or Agriculture or Engineering Graphics or Business Studies or Electronics or Entrepreneurship. Student should have obtained at least 50% marks in the above subjects taken together and must obtain an equivalence certificate from the Association of Indian Universities (AIU).
The application format is available on the AIU website link: https://evaluation.aiu.ac.in/Student/EHome
All foreign qualifications need to be verified by the AIU by the candidate before seeking provisional admission.
To promote international understanding between Indian and Foreign candidates, SSPU has reserved seats for NRIs/International candidates in every division (Supernumerary Quota).
Qualifying score in JEE or Symbiosis Engineering Entrance Test (SEET) conducted by SSPU.
Candidates will be selected based on the entrance test conducted by SSPU.
Lateral Entry for Second Year
Passed Minimum THREE years / TWO years (Lateral Entry) Diploma examination with at least 50% marks (at least 45% marks, in case of reserved categories, EWS & PWD Students belonging to Maharashtra state only) (Respective Council) in ANY branch of Engineering and Technology.
OR
Passed B.Sc. Degree from a recognized University as defined by UGC, with at least 50% marks (at least 45% marks, in case of reserved categories, EWS & PWD Students belonging to Maharashtra state only) as per guidelines of UGC / AICTE / Respective Council) and passed 10+2 examination with Mathematics as a subject.
OR
Passed B. Voc./3 yrs, D. Voc. Stream in the same or allied sector. (The Universities will offer suitable bridge courses such as Mathematics, Physics, Engineering drawing, etc., for the students coming from diverse backgrounds to achieve desired learning outcomes of the programme) Refer to table 1.10 of Appendix – 1
Note: Lateral Entry admission will be subject to a minimum of 60% course mapping and/or as per Annexure I.
Global Semiconductor Companies
- Intel – Microprocessor and chip design, AI accelerators
- AMD – CPU, GPU, and custom SoC design
- NVIDIA – GPU, AI, and deep learning hardware design
- Qualcomm – Wireless, mobile SoC, and RF IC design
- Texas Instruments – Analog, mixed-signal, and embedded IC design
- Broadcom – Networking, connectivity, and storage chip design
- Marvell Technology – Storage, networking, and semiconductor solutions
- Micron Technology – Memory and storage device design
Indian Semiconductor & Fabless Companies
- Cadence Design Systems (India) – EDA tools and chip design services
- SiValley / Synopsys (India) – Verification and EDA tool development
- AlphaWave Semi – High-performance chip design for communications
- Sapphire / SmartDV – IP cores and verification solutions
- MosChip / Ineda Systems – Low-power SoC and embedded design
- Tejas Networks – Telecom semiconductor and optical systems
OSAT & ATMP Companies
- STATS ChipPAC – Advanced packaging and testing
- Amkor Technology – Semiconductor assembly and test
- ASE Group – Outsourced semiconductor assembly & test
- GlobalFoundries (Advanced Packaging units) – Chip testing and packaging
Global Capability Centers (GCCs) in India
- Intel India GCC – R&D and design verification
- NXP Semiconductors India – Embedded systems and automotive ICs
- Marvell Technology India – Chip design and validation
- Texas Instruments India – Analog/mixed-signal design and applications
Research & Academic Opportunities
- Indian Institutes of Technology (IITs) and IISc Bangalore – Research labs for chip design and nanoelectronics
- DRDO / ISRO – Semiconductor and embedded systems research
- CSIR Labs – VLSI, MEMS, and sensor design
Startups & Deep-Tech Ventures
- Emerging chip design startups in AI accelerators, IoT devices, automotive electronics, and semiconductor IP development
Fee Details
1st Year (New Admission)
| Caution Money | Academic Fees | Total Fees | 1st Installments | 2nd Installments |
|---|---|---|---|---|
| At the time of Admission | Due Date – 31-10-2026 | |||
| ₹10,000 | ₹2,94,500 | ₹3,04,500 | ₹1,64,500 | ₹1,40,000 |
Hostel Charges
| 1 | 2 Seater Non-AC Rooms | 2,05,000 |
| 2 | Hostel Caution Money (Refundable) | 15,000 |
1st Year (New Admission)
| Caution Money | Academic Fees | Total Fees | 1st Installments | 2nd Installments |
|---|---|---|---|---|
| At the time of Admission | Due Date – 31-10-2026 | |||
| ₹10,000 | ₹3,49,500 | ₹3,59,500 | ₹1,92,000 | ₹1,67,500 |
2nd Year Onwards (Existing Students)
| Academic Fees | 1st Installments | 2nd Installments |
| Due Date – 31-07-2026 | Due Date – 31-10-2026 | |
| ₹3,49,500 | ₹1,82,000 | ₹1,67,500 |
Hostel Charges
| 1 | 2 Seater Non-AC Rooms | 2,05,000 |
| 2 | Hostel Caution Money (Refundable) | 15,000 |
Note 1 : The University shall remit the NSDC Certification Fees to NSDC and Ethnotech
Note 2 : The academic fee may be increased up to 10% each year, as per the University policy and at the discretion of the Management.
Future Opportunities
Career Pathways & Professional Growth
Graduates of the B. Tech Semiconductor Engineering can pursue high-demand roles in chip design, verification, testing, and R&D. Key roles include:
| Job Role | Description |
|---|---|
| VLSI Design Engineer (Analog / Digital / Mixed-Signal) | Designs integrated circuits, develops RTL code, simulates and optimizes performance, power, and area for chips. |
| Physical Design & Verification Engineer | Converts RTL designs to silicon layouts, performs timing analysis, floorplanning, placement & routing, and verifies functionality. |
| Test & Validation Engineer | Creates test plans, validates chip functionality, ensures reliability and performance, and supports debugging of silicon. |
| EDA Tool/Application Engineer | Supports semiconductor teams in deploying, customizing, and troubleshooting Electronic Design Automation (EDA) tools for design workflows. |
| ASIC / FPGA Engineer | Implements application-specific integrated circuits (ASICs) or FPGA designs for high-performance digital systems. |
| R&D Engineer / Scientist | Conducts research in semiconductor devices, circuits, and VLSI systems for innovation and next-generation chip development. |
| Design Verification Engineer | Develops testbenches, performs simulations, and ensures design correctness against specifications. |
| Layout & Floorplan Engineer | Focuses on physical chip layout, optimizing area, performance, and manufacturability. |
| Low-Power Design Engineer | Specializes in designing energy-efficient chips for mobile, IoT, and AI applications. |
Program Educational Objectives (PEOs)
PEO1
Graduates will apply strong foundational knowledge in semiconductor engineering to solve real-world engineering problems.
PEO2
Graduates will establish successful careers in semiconductor industries, research organizations, or pursue higher education.
PEO3
Graduates will demonstrate innovation, entrepreneurship, and adaptability in emerging semiconductor technologies.
PEO4
Graduates will exhibit professional ethics, effective communication, and teamwork in multidisciplinary environments.
PEO5
Graduates will engage in lifelong learning to stay relevant in rapidly evolving semiconductor and electronics domains.
Program Outcomes (POs)
PO1
Engineering Knowledge: Apply knowledge of mathematics, natural science, computing, engineering fundamentals and an engineering specialization as specified in WK1 to WK4 respectively to develop to the solution of complex engineering problems.
PO2
Problem Analysis: Identify, formulate, review research literature and analyze complex engineering problems reaching substantiated conclusions with consideration for sustainable development. (WK1 to WK4)
PO3
Design/Development of Solutions: Design creative solutions for complex engineering problems and design/develop systems/components/processes to meet identified needs with consideration for the public health and safety, whole-life cost, net zero carbon, culture, society and environment as required. (WK5)
PO4
Conduct Investigations of Complex Problems: Conduct investigations of complex engineering problems using research-based knowledge including design of experiments, modelling, analysis & interpretation of data to provide valid conclusions. (WK8).
PO5
Engineering Tool Usage: Create, select and apply appropriate techniques, resources and modern engineering & IT tools, including prediction and modelling recognizing their limitations to solve complex engineering problems. (WK2 and WK6)
PO6
The Engineer and The World: Analyze and evaluate societal and environmental aspects while solving complex engineering problems for its impact on sustainability with reference to economy, health, safety, legal framework, culture and environment. (WK1, WK5, and WK7).
PO7
Ethics: Apply ethical principles and commit to professional ethics, human values, diversity and inclusion; adhere to national & international laws. (WK9)
PO8
Individual and Collaborative Team work: Function effectively as an individual, and as a member or leader in diverse/multi-disciplinary teams.
PO9
Communication: Communicate effectively and inclusively within the engineering community and society at large, such as being able to comprehend and write effective reports and design documentation, make effective presentations considering cultural, language, and learning differences
PO10
Project Management and Finance: Apply knowledge and understanding of engineering management principles and economic decision-making and apply these to one’s own work, as a member and leader in a team, and to manage projects and in multidisciplinary environments
PO11
Life-Long Learning: Recognize the need for, and have the preparation and ability for i) independent and life-long learning ii) adaptability to new and emerging technologies and iii) critical thinking in the broadest context of technological change. (WK8)
Program Specific Outcomes (PSOs)

01
Ability to design and analyze semiconductor devices and integrated circuits using modern tools.
02
Ability to understand and apply semiconductor fabrication, testing, and packaging processes. Ability to develop solutions in VLSI, embedded systems, and nanoelectronics applications.
FAQs
It is an undergraduate program focusing on design, fabrication, and testing of semiconductor devices and integrated circuits.
Graduates can work in chip design, fabrication units, embedded systems, VLSI, and semiconductor manufacturing industries.
Yes, the program includes internships, lab work, and industry projects.
Students gain knowledge in electronics, materials science, chip design, and fabrication technologies.
Students can pursue M.Tech, MS, or research in semiconductor and nanoelectronics fields.
Yes, basic programming knowledge (such as C, Python, or HDL like Verilog/VHDL) is required for design and simulation.
Students must have completed 12th grade with Physics, Chemistry, and Mathematics (PCM) from a recognized board.
Students learn tools such as CAD for VLSI design, simulation software, and circuit design platforms.
The program is typically of 4 years, divided into 8 semesters.
Electronics engineering covers a broad range of electronic systems, while semiconductor engineering focuses specifically on chip design, fabrication, and materials.
Yes, internships are usually a mandatory part of the curriculum to provide industry exposure.
Industries such as electronics manufacturing, chip design companies, telecommunications, automotive electronics, and IT sectors hire graduates.
VLSI (Very Large Scale Integration) design involves creating integrated circuits by combining thousands or millions of transistors into a single chip.
Yes, there is significant scope in areas like nanoelectronics, quantum devices, and advanced semiconductor materials.
They can work as design engineers, process engineers, test engineers, fabrication engineers, or research scientists.